An outlook on Agile Hardware Development Methodology for accelerating full-stack development of Deep Learning SoCs

In modern Deep Learning accelerators, the computer architecture used to train a deep learning model affects the model’s accuracy, speed and even its ability to generalise to new data. This creates a massive multi-dimensional design space to find pareto-optimal configuration per use-case. Additionally, new ISAs need new software and compilers. How do we navigate this maze of infinite possibilities? What is Agile development for hardware all about?